3D Interconnect / Thin Wafer

The GIGAfab A200/300 plasma system is used in photoresist removal and descum technology for 3D IC and Wafer Level Packaging (WLP), in wafer bumping production lines. As 3D technology in semiconductor packaging evolves the scope of applications widens. With lessons learned from chip packaging on oxide removal of bond pads for copper wire bonding, or surface cleaning and activation prior molding and underfill PVA TePla is one of the few companies in the world that can merge typical semiconductor packaging process requirements with front end equipment design for wafer level processes with its stringent demands on particle count, scalability and a strong focus on cost of ownership.

Thin Wafer

Copper TSV, 3D Interconnect  for telecomunication devices

On top of all challenges in 3D Packaging, 2.5D and 3D technology call for stacking of thin die / wafer on top of each other to gain the benefits of decreased form factor, higher bandwidth, density and performance for mobile devices amongst others. To improve yield and reliability on ultra thin wafer (UTW) / crack die issues, backside stress relief (BSR) and chip side healing (CSH) have proved to be successful by using a 12” capable GIGAFab ASYNTIS® from PVA TePla AG.


Conventional wafer thinning and dicing processes leave process marks (kerfs, chipping, micro cracks) on the wafer back side and edge of the chip causing a significant reduction in die strength, impacting process yield during handling.
Die strength improvement on fully processed ultra thin wafers followed by plasma stress relief processes (BSR + CSH), removing additional 2-3µm of surface roughness and rounding-off wafer thinning and dicing induced defects is ready for production.