Shear Stress in Wafers
The latest design rules for semiconductors put more stringent requirement on the quality of the bare wafer material. This relates to crystal defects near the surface, which will carry the active device area. One possibility to monitor the wafer quality is to measure the stress level in order to detect micro-defects coming from abrasive or high temperature processing such as polishing or growing of epitaxial layers.
Shear Stress in Devices
Advanced packaging technologies and assembly techniques have also put emphasis on shear stress on the device level. The SIRD technique does not offer the required resolution to cope with this task. The solution is a well focused laser beam used in reflective mode called SIREX.
Implant Process Monitoring
The doping level of a device area determines its functionality. Hence it is mandatory to monitor the quality of implantation as one of the critical process steps to apply or change the doping of a device region.
Trace Metal Contamination Detection
The latest design rules for semiconductors put more stringent requirement on the presence of trace metal contamination on the wafer and in semiconductor processes and equipment. Hence the cleanliness of the wafer fab, the wafer and the interior of the many different types of process equipment becomes more and more critical. Our Surface contamination technique allows tracing unwanted elements to the level of 1E7 atoms/cm² and even lower.
A very well-known method is the use of ultra-sonic energy and its reflections in areas of different density. In combination with high frequency provided by the PVA Tepla proprietary tranducer technology this technique allows pictures of defects in wafers, ingots and packaged devices with very good resolution.